Enable the mmio mux driver, the J721E-wiz PHy driver and the cadence sierra
phy driver. All of them are required for USB3 support

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Partially sync with Linux's dts to add the entries required for USB3
support on USB0.
Note that the default mode is still "peripheral" not "host". USB3 is
supported only for the host mode.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES
wrapper used to configure some of the input signals to the SERDES. It is
used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures
three clock selects (pll0, pll1, dig) and supports resets for each of the
lanes.

This is an adaptation of the linux driver.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
wiz (wip)
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

This squashes several changes available in the TI linux tree:
phy: cadence: Sierra: add phy_reset hook
phy: cadence: Sierra: Set cmn_refclk/cmn_refclk1 frequency to 25MHz
phy: cadence: Sierra: Change MAX_LANES of Sierra to 16
phy: cadence: Sierra: Check for PLL lock during PHY power on
phy: cadence: Sierra: Get reset control "array" for each link
phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC
phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide
phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops
phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC
phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers
phy: cadence: Sierra: Make "clock" and "reset" optional resources

One difference with the linux driver is that the PHY is always reset after
it is powered-on. This is because role switching is not supported in u-boot
and the cable orientation is handled by the PHY reset

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add a Sierra PHY driver with PCIe and USB support.
This driver is a port from the mainline linux driver (v5.2).

The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.

There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself.  Additionally there are
resets for each PHY lane.

The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.

The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required)  for each lane
group, and then enable the PHY.  Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY

Signed-off-by: Alan Douglas <adouglas@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

This adds a driver for mmio-based syscon multiplexers controlled by
bitfields in a syscon register range.
This is heavily based on the linux mmio-mux driver.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

This will probe the multiplexer devices that have a "u-boot,mux-autoprobe"
property. As a consequence they will be put in their idle state.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add a new subsystem that handles multiplexer controllers. The API is the
same as in Linux.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add managed functions to get a gpio from the devce-tree, based on a
property name (minus the '-gpios' suffix) and optionally an index.

When the device is unbound, the GPIO is automatically released and the
data structure is freed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Prepare the way for a managed GPIO API by handling NULL pointers without
crashing nor failing.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add managed functions to get a reset_ctl from the device-tree, based on a
name or an index.
Also add a managed functions to get a reset_ctl_bulk (array of reset_ctl)
from the device-tree.

When the device is unbound, the reset controllers are automatically
released and the data structure is freed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Prepare the way for a managed reset API by handling NULL pointers without
crashing nor failing.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

A regmap field is an abstraction available in Linux. It provides to access
bitfields in a regmap without having to worry about shifts and masks.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Some linux drivers provide their own read/write functions to access data
from/of the regmap. Adding support for it.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Most of new linux drivers are using managed-API to allocate resources. To
ease porting drivers from linux to u-boot, introduce devm_regmap_init() as
a managed API to get a regmap from the device tree.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

The latest data manual SPRSP08I –NOVEMBER 2017–REVISED DECEMBER 2019[1]
for am65xx SoC states the new MPU nominal voltages to be 1.1V (OPP_NOM),
1.2V (OPP_OD) and 1.24V (OPP_TURBO). Update the nominal voltages in the
K3 AVS driver to reflect this.

[1] http://www.ti.com/lit/gpn/am6528



Signed-off-by: Tero Kristo <t-kristo@ti.com>

The boot parameter table index memory address for J721E was configured
to an incorrect value which prevented the use of this definition to
determine which boot parameter table is active which is needed to be
able to distinguish between primary and backup boot modes. Fix this
issue by updating the value to the correct one also in alignment with
the J721E Technical Reference Manual (TRM).

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Activate early console functionality on AM65x devices to allow for
early diagnostic messages until the main console is ready
to get activated.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

The R5F subsystem/cluster on K3 SoCs can support both LockStep and
Split-modes (superset) or just Split-mode depending on an eFUSE
capability register. The LockStep configuration bit is Read-only
though on Split-mode _only_ devices and as such the System Firmware
does not allow the LockStep mode bit to be configured on such devices.
The current logic in k3_r5f_rproc_configure() fails on Split-mode
devices because of this unconditional programming of the LockStep
mode bit, and results in the probe failure shown during the
"rproc init" step at U-Boot prompt.

Fix this by limiting the LockStep mode bit clear configuration only on
devices supporting both LockStep/Split-modes.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Add k3-j721e-common-proc-board-infotainment.dtbo reference for
J7X-INFOTAN-EXP.

Signed-off-by: Benoit Parrot <bparrot@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

Add the idk overlay. This has only the prueth nodes as the
m_can base nodes are not defined in u-boot. This is not the
same as kernel dtso.

Signed-off-by: Keerthy <j-keerthy@ti.com>

Add the ICCSG0/1 and child nodes.

Signed-off-by: Keerthy <j-keerthy@ti.com>

The bind function is already present in the misc layer.
Hence remove the duplication in the pruss driver.

Signed-off-by: Keerthy <j-keerthy@ti.com>

The am335x-ice-v2 board's Ethernet ports can be configured
in 'MII' or 'RMII' mode to be connected to 'PRUSS' or 'CPSW'
Ethernet subsystems.

This patch sets the environment variable 'ice_mii' to
'mii' or 'rmii' accordingly. Based on that we choose the
appropriate board devicetree i.e. 'am335x-ice-v2.dtb' or
'am335x-ice-v2-prueth.dtb'.

Since there are 2 Ethernet ports with 2 modes, there can be 4
configurations but for now we consider both ports in different modes
to be an invalid configuration and prevent boot in that case.

Signed-off-by: Roger Quadros <rogerq@ti.com>

The board file sets the 'idk_lcd' environment variable based on
what LCD panel was detected. We just need to choose the right
DTB based on that.

Signed-off-by: Roger Quadros <rogerq@ti.com>

On am571x-idk there can be following configurations based on Jumper J51
and LCD panel detected.

1) J51 removed (6port): 6 port Ethernet. Disable LCD panel.
2) J51 placed (LCD) + Panel detected: 4 port Ethernet with appropriate LCD.
3) J51 placed (LCD) + Panel not detected/not supported.

Configuration 3 is considered invalid as we can't use display nor ICSS1
ethernet ports due to hardware muxing. Alert the user to fix the
configuration and prevent boot.

Alternative was to allow boot and limit to 4 port Ethernet with no display
but this involved introduction of another DTB for the kernel and was
considered not worth the hassle.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Suman Anna <s-anna@ti.com>

commit 53714c5b upstream.

The CORE_TEMP_SENSOR_MPU register gives a raw adc value which needs to
be indexed into a lookup table to get the actual temperature. Fix the
naming and datatype of the adc value variable.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>

Update the default dtbs for AM57xx EVM:s to map to AM57xx EVM
specific dtbs, instead of the beagle-x15 ones.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>

Enable ESM modules for both PMIC and SoC side for proper watchdog
handling on the board.

Signed-off-by: Tero Kristo <t-kristo@ti.com>

Initialize both ESM and ESM_PMIC support if available for the board.
If support is not available for either, a warning is printed out.

Signed-off-by: Tero Kristo <t-kristo@ti.com>

The ESM handling on J7 processor board requires routing the
MCU_SAFETY_ERROR signal to the PMIC on the board for critical safety
error handling. The PMIC itself should then reset the board based on
receiving it. Enable the support for the board by adding the esm
node in place.

Signed-off-by: Tero Kristo <t-kristo@ti.com>

Main domain ESM support is needed to configure main domain watchdogs
to generate ESM pin events by default. On J7 processor board these
propagate to the PMIC to generate a reset when watchdog expires.

Signed-off-by: Tero Kristo <t-kristo@ti.com>

The ESM (Error Signal Monitor) is used on certain PMIC versions to
handle error signals propagating from rest of the system. If these
reach the PMIC, it is typically a last resort fatal error which
requires a system reset. The ESM driver does the proper configuration
for the ESM module to reach this end goal. Initially, only TPS65941
PMIC is supported for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>

The ESM (Error Signaling Module) is used to route error signals within
the K3 SoCs somewhat similar to interrupts. The handling for these is
different though, and can be routed for hardware error handling, to
be handled by safety processor or just as error interrupts handled
by the main processor. The u-boot level ESM driver is just used to
configure the ESM signals so that they get routed to proper destination.

Signed-off-by: Tero Kristo <t-kristo@ti.com>

TPS65941 can have child devices under it (like the ESM support), so
probe these once the master pmic node completes probe.

Signed-off-by: Tero Kristo <t-kristo@ti.com>

MLO has increased to a size greater than the allocated
128 kB in dfu_alt_info_emmc and _mmc.

Therefore, double the allocated size for MLO.raw in
the default environment.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>

commit 53dc8ae6 upstream.

GCC 9.x starts complaining about potential misalignment of the pointer to
the array (in this case alignment=2) in the packed (alignment=1) structures.

Repeating Linus' Torvalds commit 6f303d60534c in the Linux kernel.

Original commit message:

  We already did this for clang, but now gcc has that warning too.
  Yes, yes, the address may be unaligned.  And that's kind of the point.

This in particular hides the warnings like

drivers/usb/gadget/composite.c:545:23: warning: taking address of packed member of ‘struct usb_string_descriptor’ may result in an unaligned pointer value [-Waddress-of-packed-member]
  545 |    collect_langs(sp, s->wData);

drivers/usb/gadget/composite.c:550:24: warning: taking address of packed member of ‘struct usb_string_descriptor’ may result in an unaligned pointer value [-Waddress-of-packed-member]
  550 |     collect_langs(sp, s->wData);

drivers/usb/gadget/composite.c:555:25: warning: taking address of packed member of ‘struct usb_string_descriptor’ may result in an unaligned pointer value [-Waddress-of-packed-member]
  555 |      collect_langs(sp, s->wData);

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Data manual mentions the new silicon revisions as SR instead of PG. Use
the same nomenclature inside U-Boot as well.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Configure NAVSS NB to that order IDs >= 8 are treated as real-time
traffic.

RT transactions should have order ID >= 8, and the maximum order ID is
15. This patch uses a simple scheme where each DSS channel is assigned
an order ID counting down from 15.

The result is that VID and VIDL pipes get a channel ID between 0x8 and
0xf, and WB gets channel ID 6 and 7.

Each pipe has a separate order ID to allow more parallelism when
fetching the pixel data.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

NB0 is bridge to SRAM and NB1 is bridge to DDR.

To ensure that SRAM transfers are not stalled due to
delays during DDR refreshes, SRAM traffic should be higher
priority (threadmap=2) than DDR traffic (threadmap=0).

This patch does just that.

This is required to fix ICSSG TX lock-ups due to delays in
MSMC transfers due to incorrect Northbridge configuration.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Benoit Parrot <bparrot@ti.com>