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Commit 80aeacd0 authored by Drew Fustini's avatar Drew Fustini
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DO_NOT_MERGE soc: build Foobar SoC drivers

Add Foobar SoC cache and memory controller drivers to the build.

The hypothetical Foobar SoC serves as an example of an SoC with
controllers that implement the RISC-V Capacity and Bandwidth QoS
Register Interface (CBQRI) specification.

Link: https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf


Co-developed-by: default avatarAdrien Ricciardi <aricciardi@baylibre.com>
Signed-off-by: default avatarAdrien Ricciardi <aricciardi@baylibre.com>
Signed-off-by: default avatarDrew Fustini <dfustini@baylibre.com>
parent a846aba7
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...@@ -8,6 +8,7 @@ source "drivers/soc/aspeed/Kconfig" ...@@ -8,6 +8,7 @@ source "drivers/soc/aspeed/Kconfig"
source "drivers/soc/atmel/Kconfig" source "drivers/soc/atmel/Kconfig"
source "drivers/soc/bcm/Kconfig" source "drivers/soc/bcm/Kconfig"
source "drivers/soc/canaan/Kconfig" source "drivers/soc/canaan/Kconfig"
source "drivers/soc/foobar/Kconfig"
source "drivers/soc/fsl/Kconfig" source "drivers/soc/fsl/Kconfig"
source "drivers/soc/fujitsu/Kconfig" source "drivers/soc/fujitsu/Kconfig"
source "drivers/soc/imx/Kconfig" source "drivers/soc/imx/Kconfig"
......
...@@ -11,6 +11,7 @@ obj-y += bcm/ ...@@ -11,6 +11,7 @@ obj-y += bcm/
obj-$(CONFIG_SOC_CANAAN) += canaan/ obj-$(CONFIG_SOC_CANAAN) += canaan/
obj-$(CONFIG_ARCH_DOVE) += dove/ obj-$(CONFIG_ARCH_DOVE) += dove/
obj-$(CONFIG_MACH_DOVE) += dove/ obj-$(CONFIG_MACH_DOVE) += dove/
obj-y += foobar/
obj-y += fsl/ obj-y += fsl/
obj-y += fujitsu/ obj-y += fujitsu/
obj-$(CONFIG_ARCH_GEMINI) += gemini/ obj-$(CONFIG_ARCH_GEMINI) += gemini/
......
# SPDX-License-Identifier: GPL-2.0
config FOOBAR_CBQRI_CACHE
bool "Foobar cache controller for RISC-V CBQRI testing"
default y
help
Support the cache controller in a hypothetical "Foobar" SoC that
implements the RISC-V Capacity and Bandwidth QoS Register Interface
(CBQRI) specification.
If you do not care about testing RISC-V CBQRI, then choose 'N'.
config FOOBAR_CBQRI_MEMORY
bool "Foobar memory controller for RISC-V CBQRI testing"
default y
help
Support the memory controller in a hypothetical "Foobar" SoC that
implements the RISC-V Capacity and Bandwidth QoS Register Interface
(CBQRI) specification.
If you do not care about testing RISC-V CBQRI, then choose 'N'.
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_FOOBAR_CBQRI_CACHE) += foobar_cbqri_cache.o
obj-$(CONFIG_FOOBAR_CBQRI_MEMORY) += foobar_cbqri_memory.o
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