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Drew Fustini authoredAdd Foobar SoC cache and memory controller drivers to the build. The hypothetical Foobar SoC serves as an example of an SoC with controllers that implement the RISC-V Capacity and Bandwidth QoS Register Interface (CBQRI) specification. Link: https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf Co-developed-by:
Adrien Ricciardi <aricciardi@baylibre.com> Signed-off-by:
Drew Fustini <dfustini@baylibre.com>
Drew Fustini authoredAdd Foobar SoC cache and memory controller drivers to the build. The hypothetical Foobar SoC serves as an example of an SoC with controllers that implement the RISC-V Capacity and Bandwidth QoS Register Interface (CBQRI) specification. Link: https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf Co-developed-by: