- Feb 09, 2023
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Enable DFU_MTD to allow update OSPI NAND over USB. usage wrt OSPI NAND for example: On EVM => setenv dfu_alt_info $dfu_alt_info_ospi_nand => dfu 0 mtd spi-nand0 On PC $ sudo dfu-util -l $ sudo dfu-util -a tispl.bin -D tispl.bin Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Enable DFU MTD, RAM, SF and MMC to allow update of respective media over USB. Usage wrt OSPI NAND for example: => setenv dfu_alt_info $dfu_alt_info_ospi_nand => dfu 0 mtd spi-nand0 On PC $ sudo dfu-util -l $ sudo dfu-util -a tispl.bin -D tispl.bin Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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AM62x LP SK and AM62A SK have OSPI NAND on board, add DFU entries for the same. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Define dfu_alt_info settings for OSPI NAND to enable flashing to OSPI NAND flash via USB Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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On security enforced (HS-SE) devices ROM firewalls OSPI data region3 that is present in above 64bit region. Open this up in bootloader to allow Linux to access OSPI flashes in mmap mode. Without this kernel will crash when accessing this region due to firewall violations on HS-SE devices. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Tested-by:
Judith Mendez <jm@ti.com>
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Updates to HyperBus calibration sequence requires the HBMC config register region, include that in hbmc node. Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by:
Siddharth Vadapalli <s-vadapalli@ti.com>
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Updates to HyperBus calibration sequence requires the HBMC config register region, include that in hbmc node. Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by:
Siddharth Vadapalli <s-vadapalli@ti.com>
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Update the HyperBus calibration sequence to fix the instabilities seen during calibration.The current calibration sequence is same as described in J721E TRM[1] which is as follows: 1) Ensure FIFO RAM Auto-init is complete 2) Attempt to read 64 bytes of data from CFI region for 16 iterations and if data is same in 4 successive iterations then consider Delay Locked Loop(DLL) is stabilized. 3) Verify DLL lock by verifying MDLL_LOCK and SDL_LOCK bit set in CFG_DLL_STAT register. 4) Confirm calibration by checking for "QRY" string in CFI region. Also perform minor cleanup and update am654_hyperbus_calibrate() to return non-zero value on failure. Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by:
Siddharth Vadapalli <s-vadapalli@ti.com>
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The u-boot SoC specific dtsi files are updated to align with Kernel. Update the j784s4 evm DT files to accomodate those change made to the dtsi files. Signed-off-by:
Dasnavis Sabiya <sabiya.d@ti.com> Tested-by:
Hari Nagalla <hnagalla@ti.com> Reviewed-by:
Siddharth Vadapalli <s-vadapalli@ti.com>
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The u-boot DT files need to be in sync with kernel DT files. Update the SoC specific DT files to match the label, node names and add the missing nodes to be in sync with the kernel files. The List of updates in the k3-j784s4-main.dtsi file: * The nodes and child nodes of system-controller * The node name of hwlock * The nodes and child nodes of the main_cpsw0 and main_cpsw1 The List of updates in the k3-j784s4-mcu-wakeup.dtsi file: * Label name of mcu_cpsw_port1 Signed-off-by:
Dasnavis Sabiya <sabiya.d@ti.com> Tested-by:
Hari Nagalla <hnagalla@ti.com> Reviewed-by:
Siddharth Vadapalli <s-vadapalli@ti.com>
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Enable GPIO, I2C for raw manipulations of GPIO pins and I2C devices CMD_DM shows state of device/drivers in the system which is useful to debugging. CMD_TIME helps to measure performance Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Enable configs required to support OSPI NAND at A53 SPL and U-Boot Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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This rearranges configs as required, to easy additional new config options Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Enable configs required to support OSPI NAND boot. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Update stack, heap size to max available memory, without this R5 SPL DT gets corrupted in certain boot modes Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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User can specify/override the NAND partition and UBIFS volume for booting via ${nbootpart} and ${nbootvolume} variables respectively. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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AM62A SK has a W35 OSPI NAND connected to OSPI controller. Add DT nodes for the same. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Use more conventional naming scheme for NAND partitions and enable listing of partitions in prompt. Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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User can specify/override the NAND partition and UBIFS volume for booting via ${nbootpart} and ${nbootvolume} variables respectively. Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Flash settings such as Octal-DTR mode and other register configurations should be resetted before the flash is removed. This would enable a clean removal and re-plug for later boot stages. The soft-reset command doesn't restore the flash into 1S mode, so add support for executing 66h+99h PoR flash reset when in Octal DTR mode. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Releasing the flash into proper state, after the loading completes, is important for the next stage bootloader/kernel to be able to use the MTD device. This would enable to reset the device for fresh use by next boot stage. Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Winbond W35N01JW is a SPI NAND flash supporting Octal DTR SPI protocol. Add op_variants and ctrl_ops_variants for W35N01JW, thus adding all required Octal DTR ops. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Add implementation of change_protocol() for Winbond's manufacturer_ops, that executes octal_dtr_enable() and octal_dtr_disable() according to requested protocol. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Add implementation of octal_dtr_enable() and octal_dtr_disable() manufacturer_ops for Winbond. To switch to Ocatl DTR mode, setting programmable dummy cycles and SPI IO mode using the volatile configuration register is required. To function at max 120MHz SPI clock in Octal DTR mode, 12 programmable dummy clock cycle setting is required. (Default number of dummy cycle are 8 clocks) Set the programmable dummy cycle to 12 clocks, and SPI IO mode to Octal DTR with Data Strobe in the VCR. Also, perform a READ ID operation in Octal DTR SPI mode to ensure the switch was successful. To disable Octal DTR mode, restore the VCR registers to their default values and verify it using READ ID operation. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Volatile configuration register are a different set of configuration registers, i.e. they differ from the status registers. A different SPI instruction is required to write to these registers. Any changes to the Volatile Configuration Register get transferred directly to the Internal Configuration Register and instantly reflect on the device operation. In Winbond W35N01JW, these volatile configuration register must be configured in order to switch to Octal DTR SPI mode. Add support for writing to volatile configuration registers using a new WRITE_VCR_OP template. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Enable Octal DTR SPI mode, i.e. 8D-8D-8D mode, if the SPI NAND flash device supports it. Mixed OSPI (1S-1S-8S & 1S-8S-8S), mixed DTR modes (1S-1D-8D), etc. aren't supported yet. The method to switch to Octal DTR SPI mode may vary across manufacturers. For example, for Winbond, it is enabled by writing values to the volatile configuration register. So, let the manufacturer's code have their own implementation for switching to Octal DTR SPI mode. Check for the SPI NAND device's support for Octal DTR mode using spinand flags, and if the data_ops and ctrl_ops are 8D-8D-8D, call change_mode() manufacturer op. If the SPI controller doesn't supports these modes, the selected data_ops and ctrl_ops will prevent switching to the Octal DTR mode. And finally update the spinand protocol and ctrl_ops on success. Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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The data_ops_variants and ctrl_ops_variants defined in manufacturer's code are required again when changing flash modes, because they hold the op templates for the new protocol. It would be useful to have a pointer to the device description entry i.e. probed flash's spinand_info table in the spinand_device struct itself. Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Introduce change_protocol() manufacturer_op to let the vendor provide the implementation of switching of SPI IO modes. The method to switch to different SPI IO mode may vary across manufacturers. For example, for Winbond, Octal DTR is enabled by writing values to the volatile configuration register. So, let the manufacturer's code have their own implementation for switching to any given SPI IO mode. Manufacturer's code need to take care, if the requested protocol change is allowed/needed and how to apply it. Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Add ctrl_ops_variants, which can be used by the manufacturers' codes to define their SPI control operation variants. Add a macro to easily define ctrl_ops_varinats. This can be used to list out all the supported ctrl ops with their respective protocols by the vendors. Add spinand_select_ctrl_ops_variant() helper function to search for a supported ctrl_ops variant with the required SPI protocol in a given list of variants. Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Make use of the ctrl_ops struct, to introduce the usage of templates in non-page read/write operations as well. These templates are initialized at the probe time or at SPI modes switches. Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Add default ctrl_ops in the core, which can be used when the op templates are commonly used ones. Till now, the core had used only fixed ctrl operations, so the default 'ctrl_ops' is just these ops macros initialized with default arguments. The default protocol is 1S-1S-1S. Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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'ctrl_ops' are op templates for non-page read/write operations, which are: reset, get_feature, set_feature, write_enable, block_erase, page_read and program_execute ops. The 'ctrl_ops' struct contains in it op templates for each of this op, as well as enum spinand_protocol denoting protocol of all these ops. We require these new op templates because of deviation in standard SPINAND ops by manufacturers and also due to changes when there is a change in SPI protocol/mode. This prevents the core from live-patching and vendor-specific adjustments in ops. Define 'ctrl_ops', add macros to initialize it and add it in spinand_device. Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Manufacturers have been deviating from the standard SPI operations for NAND flashes. There have been variations in non-page read/write instructions too. Additionally, operations, including non-page r/w ops, vary when flash is in different SPI mode, eg. Octal DTR. To avoid live-patching in hot-paths or vendor-specific adjustment, it is better to have a set of operation templates and variants for non-page read/write operations as well. These would get initialized at the probe time or when flash changes modes. These would be called 'ctrl_ops'. To make code better understandable, create two types of op templates which are: data_ops and ctrl_ops. Reason for having two different type of templates is the difference in their use cases i.e. it is possible to have ops of different protocol for read/write/update simulatneously in the data_ops, but all the ops in the ctrl_ops follow same protocol. Rename op_templates to data_ops, and the ctrl_ops would be introduced in later commits. Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Unlike Dual and Quad SPI modes flashes, Octal DTR SPI NAND flashes require all instructions to be made in 8D-8D-8D protocol when the flash is in Octal DTR mode. Hence, storing the current SPI IO mode becomes necessary for operating the flash and switching between modes. Store the current SPI IO mode in the spinand struct using a spinand_protocol enum. This would act as a flag, denoting that the core should use the given SPI protocol all types of flash operations. Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Define new op templates for reset, write enable, set_feature, get_feature, block_erase, read/write page operations for Octal DTR SPI mode. These templates will be used in data_ops and ctrl_ops for performing all flash operations. Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Setting dtr field of spi_mem_op is used when creating templates for DTR ops in spinand.h. Also, 2 bytes cmd phases are required when operating in Octal DTR SPI mode. Create new templates for dtr mode cmd, address, dummy and data phase in spi_mem_op, to set the dtr field to 1 and also allow passing the nbytes for the cmd phase. Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset the cache content to 0xFF (depends on vendor implementation), so we must fill the page cache entirely even if we only want to program the data portion of the page, otherwise we might corrupt the BBM or user data previously programmed in OOB area. commit mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache ("13c15e07eedf26092054c8c71f2f47edb8388310") Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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OSPI controller supports all types of op variants in STIG mode, only limitation being that the data payload should be less than 8 bytes when not using memory banks. STIG mode is more stable for operations that send small data payload and is more efficient than using DMA for few bytes of memory accesses. It overcomes the limitation of minimum 4 bytes read from flash into RAM seen in DAC mode. Use STIG mode for all read and write operations that require data input/output of less than 8 bytes from the flash, and thereby support all four phases, cmd/address/dummy/data, through OSPI STIG. Signed-off-by:
Apurva Nandan <a-nandan@ti.com> Reviewed-by:
Dhruva Gole <d-gole@ti.com>
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buswidth and dtr fields in spi_mem_op are only valid when the corresponding spi_mem_op phase has a non-zero length. For example, SPI NAND core doesn't set buswidth when using SPI_MEM_OP_NO_ADDR phase. Fix the dtr checks in set_protocol() to ignore empty spi_mem_op phases, as checking for dtr field in empty phase will result in false negatives. Signed-off-by:
Apurva Nandan <a-nandan@ti.com> Reviewed-by:
Dhruva Gole <d-gole@ti.com>
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The u-boot ums command models the EVM as a card reader and shows the SD Card latched on the evm as a memory device in the host PC. The Type - C dual role port should be used for this functionality. This helps in automating the linux debugging process. Enable this command in the defconfig. Signed-off-by:
Aradhya Bhatia <a-bhatia1@ti.com>
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