- Jul 27, 2022
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Richard Henderson authored
Signed-off-by:Richard Henderson <richard.henderson@linaro.org>
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- Jul 26, 2022
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git://git.kernel.org/pub/scm/virt/kvm/mst/qemuRichard Henderson authored
pc,virtio: fixes Several fixes. From now on, regression fixes only. Signed-off-by:
Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmLgQr8PHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpGUUIAKtNhrnKopGm4LlRpx8zN3Jc1Jo0nb648gaM # Oyi+Pl8+hpESUhaWN10XDk38/QuPQfIFeR2ZhfYjFTRlZE+n3X9LVlwL8ejjP8KH # AcWm78Ff/SLA45aMKMmw74pvEDNsoPYTp7TrfeIej5ub8BIXr8+8pqDdIR9WwtWO # PbhLNXkTT2yLEs6jCVT4/dyh7zivSkrY7G/RVmtUaFe3PgY8fdW2z3+Txz7UIMgw # CQoGuAucCO5ToBbs2CbT0V5yxY6G5VO6Qd8g0PzDW4M6GsY/Xr5QCnyJe0jTW0d6 # Dcc7UZFAzGNzyQCxHCic9xwTO+ZcJPJlH5TwknunxOb9xwCx4Qs= # =zN41 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 26 Jul 2022 12:38:39 PM PDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [undefined] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu : hw/virtio/virtio-iommu: Enforce power-of-two notify for both MAP and UNMAP i386/pc: restrict AMD only enforcing of 1Tb hole to new machine type i386/pc: relocate 4g start to 1T where applicable i386/pc: bounds check phys-bits against max used GPA i386/pc: factor out device_memory base/size to helper i386/pc: handle unitialized mr in pc_get_cxl_range_end() i386/pc: factor out cxl range start to helper i386/pc: factor out cxl range end to helper i386/pc: factor out above-4g end to an helper i386/pc: pass pci_hole64_size to pc_memory_init() i386/pc: create pci-host qdev prior to pc_memory_init() hw/i386: add 4g boundary start to X86MachineState hw/cxl: Fix size of constant in interleave granularity function. hw/i386/pc: Always place CXL Memory Regions after device_memory hw/machine: Clear out left over CXL related pointer from move of state handling to machines. acpi/nvdimm: Define trace events for NVDIMM and substitute nvdimm_debug() Signed-off-by:
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Jean-Philippe Brucker authored
Currently we only enforce power-of-two mappings (required by the QEMU notifier) for UNMAP requests. A MAP request not aligned on a power-of-two may be successfully handled by VFIO, and then the corresponding UNMAP notify will fail because it will attempt to split that mapping. Ensure MAP and UNMAP notifications are consistent. Fixes: dde3f08b ("virtio-iommu: Handle non power of 2 range invalidations") Reported-by:
Tina Zhang <tina.zhang@intel.com> Signed-off-by:
Jean-Philippe Brucker <jean-philippe@linaro.org> Message-Id: <20220718135636.338264-1-jean-philippe@linaro.org> Tested-by:
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Richard Henderson authored
Merge tag 'pull-target-arm-20220726' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Update Coverity component definitions * target/arm: Add MO_128 entry to pred_esz_masks[] * configure: Fix portability issues * hw/display/bcm2835_fb: Fix framebuffer allocation address # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmLgBfkZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3vFdD/wLVC2gJ4Uxt2Ri5vutF6fl # RKTNiIhcE/XQNUogQiVIERYJJ9CUOALtg3q/SPCItq0nFgNG4h+sB7Ms+VcYVmNd # iphbYBF4nFXYsAGlYIiAPU4I5SVnL4ORLMovRmlqMGYO/xlWe4LMIIOI+Iky4z9G # pgho7n0yuKNPwikFdX1nKH2lYvoh9pn/p8buwre4qg6z/p4XssV295NAWeGvynab # Sj9cmBvQC9ijKADvWXrfaGbHWQCAOwjRI7su/Ky0QGHjEprBpyCC8QtKEPP0flTh # ffWCPX/pATwkbOH6m7rVFhIpI0r+6UQaDX/5SWruMNRto6WocNbX3JYT4XzdNln9 # nkVTgqn5PTzfd801RmfhJ/iGV2zf3ZE/Entj3n1RrpxI1gb56Q2tFghJNVgnL4Mq # eBeODhPUJRqOd2dIcFKQbRhQs4Uaonu4V6QM+F7SekdV7VbU5VbJzB/9IvCkpNJo # TqHDLp3makEabonal2gucmhxon7+C+4NXv+YMzTQbG2g/lVa4kmXehEA5BDcFScE # XYKBEXkWsabV2IRVaZybu+0qkD+2PNtWQP3iAqOX8RPCGKieu4fbDTbzaPJAPNTb # OBgDnzO3tukwI1upHQDIuO06poGfwMjJGKR4IZgCphTzNO7AtzUBFR96wmoaJGfq # t7VO2lnKf5tGPifFTi/egg== # =SWMq # -----END PGP SIGNATURE----- # gpg: Signature made Tue 26 Jul 2022 08:19:21 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20220726' of https://git.linaro.org/people/pmaydell/qemu-arm : hw/display/bcm2835_fb: Fix framebuffer allocation address configure: Avoid '==' bashism configure: Drop dead code attempting to use -msmall-data on alpha hosts configure: Don't use bash-specific string-replacement syntax configure: Add braces to clarify intent of $emu[[:space:]] configure: Add missing POSIX-required space target/arm: Add MO_128 entry to pred_esz_masks[] scripts/coverity-scan/COMPONENTS.md: Update slirp component info scripts/coverity-scan/COMPONENTS.md: Add loongarch component Signed-off-by:
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Joao Martins authored
The added enforcing is only relevant in the case of AMD where the range right before the 1TB is restricted and cannot be DMA mapped by the kernel consequently leading to IOMMU INVALID_DEVICE_REQUEST or possibly other kinds of IOMMU events in the AMD IOMMU. Although, there's a case where it may make sense to disable the IOVA relocation/validation when migrating from a non-amd-1tb-aware qemu to one that supports it. Relocating RAM regions to after the 1Tb hole has consequences for guest ABI because we are changing the memory mapping, so make sure that only new machine enforce but not older ones. Signed-off-by:
Joao Martins <joao.m.martins@oracle.com> Acked-by:
Dr. David Alan Gilbert <dgilbert@redhat.com> Acked-by:
Igor Mammedov <imammedo@redhat.com> Message-Id: <20220719170014.27028-12-joao.m.martins@oracle.com> Reviewed-by:
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Joao Martins authored
It is assumed that the whole GPA space is available to be DMA addressable, within a given address space limit, except for a tiny region before the 4G. Since Linux v5.4, VFIO validates whether the selected GPA is indeed valid i.e. not reserved by IOMMU on behalf of some specific devices or platform-defined restrictions, and thus failing the ioctl(VFIO_DMA_MAP) with -EINVAL. AMD systems with an IOMMU are examples of such platforms and particularly may only have these ranges as allowed: 0000000000000000 - 00000000fedfffff (0 .. 3.982G) 00000000fef00000 - 000000fcffffffff (3.983G .. 1011.9G) 0000010000000000 - ffffffffffffffff (1Tb .. 16Pb[*]) We already account for the 4G hole, albeit if the guest is big enough we will fail to allocate a guest with >1010G due to the ~12G hole at the 1Tb boundary, reserved for HyperTransport (HT). [*] there is another reserved region unrelated to HT that exists in the 256T boundary in Fam 17h according to Errata #1286, documeted also in "Open-Source Register Reference for AMD Family 17h Processors (PUB)" When creating the region above 4G, take into account that on AMD platforms the HyperTransport range is reserved and hence it cannot be used either as GPAs. On those cases rather than establishing the start of ram-above-4g to be 4G, relocate instead to 1Tb. See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", for more information on the underlying restriction of IOVAs. After accounting for the 1Tb hole on AMD hosts, mtree should look like: 0000000000000000-000000007fffffff (prio 0, i/o): alias ram-below-4g @pc.ram 0000000000000000-000000007fffffff 0000010000000000-000001ff7fffffff (prio 0, i/o): alias ram-above-4g @pc.ram 0000000080000000-000000ffffffffff If the relocation is done or the address space covers it, we also add the the reserved HT e820 range as reserved. Default phys-bits on Qemu is TCG_PHYS_ADDR_BITS (40) which is enough to address 1Tb (0xff ffff ffff). On AMD platforms, if a ram-above-4g relocation is attempted and the CPU wasn't configured with a big enough phys-bits, an error message will be printed due to the maxphysaddr vs maxusedaddr check previously added. Suggested-by: -
Joao Martins authored
Calculate max *used* GPA against the CPU maximum possible address and error out if the former surprasses the latter. This ensures max used GPA is reacheable by configured phys-bits. Default phys-bits on Qemu is TCG_PHYS_ADDR_BITS (40) which is enough for the CPU to address 1Tb (0xff ffff ffff) or 1010G (0xfc ffff ffff) in AMD hosts with IOMMU. This is preparation for AMD guests with >1010G, where it will want relocate ram-above-4g to be after 1Tb instead of 4G. Signed-off-by:
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Joao Martins authored
Move obtaining hole64_start from device_memory memory region base/size into an helper alongside correspondent getters in pc_memory_init() when the hotplug range is unitialized. While doing that remove the memory region based logic from this newly added helper. This is the final step that allows pc_pci_hole64_start() to be callable at the beginning of pc_memory_init() before any memory regions are initialized. Cc: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by:
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Joao Martins authored
Remove pc_get_cxl_range_end() dependency on the CXL memory region, and replace with one that does not require the CXL host_mr to determine the start of CXL start. This in preparation to allow pc_pci_hole64_start() to be called early in pc_memory_init(), handle CXL memory region end when its underlying memory region isn't yet initialized. Cc: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by:
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Joao Martins authored
Factor out the calculation of the base address of the memory region. It will be used later on for the cxl range end counterpart calculation and as well in pc_memory_init() CXL memory region initialization, thus avoiding duplication. Cc: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by:
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Joao Martins authored
Move calculation of CXL memory region end to separate helper. This is in preparation to a future change that removes CXL range dependency on the CXL memory region, with the goal of allowing pc_pci_hole64_start() to be called before any memory region are initialized. Cc: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by:
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Joao Martins authored
There's a couple of places that seem to duplicate this calculation of RAM size above the 4G boundary. Move all those to a helper function. Signed-off-by:
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Joao Martins authored
Use the pre-initialized pci-host qdev and fetch the pci-hole64-size into pc_memory_init() newly added argument. Use PCI_HOST_PROP_PCI_HOLE64_SIZE pci-host property for fetching pci-hole64-size. This is in preparation to determine that host-phys-bits are enough and for pci-hole64-size to be considered to relocate ram-above-4g to be at 1T (on AMD platforms). Signed-off-by:
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Joao Martins authored
At the start of pc_memory_init() we usually pass a range of 0..UINT64_MAX as pci_memory, when really its 2G (i440fx) or 32G (q35). To get the real user value, we need to get pci-host passed property for default pci_hole64_size. Thus to get that, create the qdev prior to memory init to better make estimations on max used/phys addr. This is in preparation to determine that host-phys-bits are enough and also for pci-hole64-size to be considered to relocate ram-above-4g to be at 1T (on AMD platforms). Signed-off-by:
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Joao Martins authored
Rather than hardcoding the 4G boundary everywhere, introduce a X86MachineState field @above_4g_mem_start and use it accordingly. This is in preparation for relocating ram-above-4g to be dynamically start at 1T on AMD platforms. Signed-off-by:
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Jonathan Cameron authored
Whilst the interleave granularity is always small enough that this isn't a real problem (much less than 4GiB) let's change the constant to ULL to fix the coverity warning. Reported-by:
Peter Maydell <peter.maydell@linaro.org> Fixes: 829de299 ("hw/cxl/component: Add utils for interleave parameter encoding/decoding") Fixes: Coverity CID 1488868 Signed-off-by:
Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20220701132300.2264-4-Jonathan.Cameron@huawei.com> Acked-by:
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Jonathan Cameron authored
Previously broken_reserved_end was taken into account, but Igor Mammedov identified that this could lead to a clash between potential RAM being mapped in the region and CXL usage. Hence always add the size of the device_memory memory region. This only affects the case where the broken_reserved_end flag was set. Fixes: 6e4e3ae9 ("hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)") Reported-by:
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Jonathan Cameron authored
This got left behind in the move of the CXL setup code from core files to the machines that support it. Link: https://gitlab.com/qemu-project/qemu/-/commit/1ebf9001fb2701e3c00b401334c8f3900a46adaa Signed-off-by:
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Robert Hoo authored
Signed-off-by:
Robert Hoo <robert.hu@linux.intel.com> Reviewed-by:
Jingqi Liu <jingqi.liu@intel.com> Message-Id: <20220704085852.330005-1-robert.hu@linux.intel.com> Reviewed-by:
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Alan Jian authored
This patch fixes the dedicated framebuffer mailbox interface by removing an unneeded offset. This means that we pick the framebuffer address in the same way that we do if the guest code uses the buffer allocate mechanism of the bcm2835_property interface (case 0x00040001: /* Allocate buffer */ in bcm2835_property.c). The documentation of this mailbox interface doesn't say anything about using parts of the request buffer address to affect the chosen framebuffer address: https://github.com/raspberrypi/firmware/wiki/Mailbox-framebuffer-interface Some baremetal applications like the Screen01/Screen02 examples from Baking Pi tutorial[1] didn't work before this patch. [1] https://www.cl.cam.ac.uk/projects/raspberrypi/tutorials/os/screen01.html Signed-off-by:
Alan Jian <alanjian85@outlook.com> Message-id: 20220725145838.8412-1-alanjian85@outlook.com [PMM: tweaked commit message] Reviewed-by:
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Peter Maydell authored
The '==' operator to test is a bashism; the standard way to copmare strings is '='. This causes dash to complain: ../../configure: 681: test: linux: unexpected operator Signed-off-by:
Thomas Huth <thuth@redhat.com> Message-id: 20220720152631.450903-6-peter.maydell@linaro.org
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Peter Maydell authored
In commit 823eb013 we moved the setting of ARCH from configure to meson.build, but we accidentally left behind one attempt to use $ARCH in configure, which was trying to add -msmall-data to the compiler flags on Alpha hosts. Since ARCH is now never set, the test always fails and we never add the flag. There isn't actually any need to use this compiler flag on Alpha: the original intent was that it would allow us to simplify our TCG codegen on that platform, but we never actually made the TCG changes that would rely on -msmall-data. Drop the effectively-dead code from configure, as we don't need it. This was spotted by shellcheck: In ./configure line 2254: case "$ARCH" in ^---^ SC2153: Possible misspelling: ARCH may not be assigned, but arch is. Signed-off-by:
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Peter Maydell authored
The variable string-replacement syntax ${var/old/new} is a bashism (though it is also supported by some other shells), and for instance does not work with the NetBSD /bin/sh, which complains: ../src/configure: 687: Syntax error: Bad substitution Replace it with a more portable sed-based approach, similar to what we already do in quote_sh(). Note that shellcheck also diagnoses this: In ./configure line 687: e=${e/'\'/'\\'} ^-----------^ SC2039: In POSIX sh, string replacement is undefined. ^-- SC1003: Want to escape a single quote? echo 'This is how it'\''s done'. ^-- SC1003: Want to escape a single quote? echo 'This is how it'\''s done'. In ./configure line 688: e=${e/\"/'\"'} ^----------^ SC2039: In POSIX sh, string replacement is undefined. Fixes: 8154f5e6 ("meson: Prefix each element of firmware path") Signed-off-by: -
Peter Maydell authored
In shell script syntax, $var[something] is not special for variable expansion: $var is expanded. However, as it can look as if it were intended to be an array element access (the correct syntax for which is ${var[something]}), shellcheck recommends using explicit braces around ${var} to clarify the intended expansion. This fixes the warning: In ./configure line 2346: if "$target_ld" -verbose 2>&1 | grep -q "^[[:space:]]*$emu[[:space:]]*$"; then ^-- SC1087: Use braces when expanding arrays, e.g. ${array[idx]} (or ${var}[.. to quiet). Signed-off-by: -
Peter Maydell authored
In commit 7d7dbf9d we added a line to the configure script which is not valid POSIX shell syntax, because it is missing a space after a '!' character. shellcheck diagnoses this: if !(GIT="$git" "$source_path/scripts/git-submodule.sh" "$git_submodules_action" "$git_submodules"); then ^-- SC1035: You are missing a required space after the !. and the OpenBSD shell will not correctly handle this without the space. Fixes: 7d7dbf9d ("configure: replace --enable/disable-git-update with --with-git-submodules") Signed-off-by:
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Peter Maydell authored
In commit 7390e0e9, we added support for SME loads and stores. Unlike SVE loads and stores, these include handling of 128-bit elements. The SME load/store functions call down into the existing sve_cont_ldst_elements() function, which uses the element size MO_* value as an index into the pred_esz_masks[] array. Because this code path now has to handle MO_128, we need to add an extra element to the array. This bug was spotted by Coverity because it meant we were reading off the end of the array. Resolves: Coverity CID 1490539, 1490541, 1490543, 1490544, 1490545, 1490546, 1490548, 1490549, 1490550, 1490551, 1490555, 1490557, 1490558, 1490560, 1490561, 1490563 Fixes: 7390e0e9 ("target/arm: Implement SME LD1, ST1") Signed-off-by:
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Peter Maydell authored
Update the regex for the slirp component now that it lives solely inside /slirp/, and note that it should be ignored in Coverity analysis (because it's a separate upstream project now, and they run Coverity on it themselves). Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com> Message-id: 20220718142310.16013-3-peter.maydell@linaro.org
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Peter Maydell authored
Add the component regex for the new loongarch target. Signed-off-by:
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https://gitlab.com/laurent_vivier/qemuPeter Maydell authored
linux-user pull request 20220726 # gpg: Signature made Tue 26 Jul 2022 10:44:29 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * tag 'linux-user-for-7.1-pull-request' of https://gitlab.com/laurent_vivier/qemu : linux-user: Use target abi_int type for pipefd[1] in pipe() linux-user: Unconditionally use pipe2() syscall linux-user/hppa: Fix segfaults on page zero Signed-off-by:
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https://github.com/jasowang/qemuPeter Maydell authored
# gpg: Signature made Tue 26 Jul 2022 09:47:24 BST # gpg: using RSA key EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * tag 'net-pull-request' of https://github.com/jasowang/qemu : vdpa: Fix memory listener deletions of iova tree vhost: Get vring base from vq, not svq e1000e: Fix possible interrupt loss when using MSI Signed-off-by:
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Eugenio Pérez authored
vhost_vdpa_listener_region_del is always deleting the first iova entry of the tree, since it's using the needle iova instead of the result's one. This was detected using a vga virtual device in the VM using vdpa SVQ. It makes some extra memory adding and deleting, so the wrong one was mapped / unmapped. This was undetected before since all the memory was mappend and unmapped totally without that device, but other conditions could trigger it too: * mem_region was with .iova = 0, .translated_addr = (correct GPA). * iova_tree_find_iova returned right result, but does not update mem_region. * iova_tree_remove always removed region with .iova = 0. Right iova were sent to the device. * Next map will fill the first region with .iova = 0, causing a mapping with the same iova and device complains, if the next action is a map. * Next unmap will cause to try to unmap again iova = 0, causing the device to complain that no region was mapped at iova = 0. Fixes: 34e3c94e ("vdpa: Add custom IOTLB translations to SVQ") Reported-by:
Lei Yang <leiyang@redhat.com> Signed-off-by:
Eugenio Pérez <eperezma@redhat.com> Signed-off-by:
Jason Wang <jasowang@redhat.com>
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Eugenio Pérez authored
The SVQ vring used idx usually match with the guest visible one, as long as all the guest buffers (GPA) maps to exactly one buffer within qemu's VA. However, as we can see in virtqueue_map_desc, a single guest buffer could map to many buffers in SVQ vring. Also, its also a mistake to rewind them at the source of migration. Since VirtQueue is able to migrate the inflight descriptors, its responsability of the destination to perform the rewind just in case it cannot report the inflight descriptors to the device. This makes easier to migrate between backends or to recover them in vhost devices that support set in flight descriptors. Fixes: 6d0b2226 ("vdpa: Adapt vhost_vdpa_get_vring_base to SVQ") Signed-off-by:
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Ake Koomsin authored
Commit "e1000e: Prevent MSI/MSI-X storms" introduced msi_causes_pending to prevent interrupt storms problem. It was tested with MSI-X. In case of MSI, the guest can rely solely on interrupts to clear ICR. Upon clearing all pending interrupts, msi_causes_pending gets cleared. However, when e1000e_itr_should_postpone() in e1000e_send_msi() returns true, MSI never gets fired by e1000e_intrmgr_on_throttling_timer() because msi_causes_pending is still set. This results in interrupt loss. To prevent this, we need to clear msi_causes_pending when MSI is going to get fired by the throttling timer. The guest can then receive interrupts eventually. Signed-off-by:
Ake Koomsin <ake@igel.co.jp> Signed-off-by:
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- Jul 25, 2022
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https://gitlab.com/bonzini/qemuPeter Maydell authored
* Bug fixes * Pass random seed to x86 and other FDT platforms # gpg: Signature made Fri 22 Jul 2022 18:26:45 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream2' of https://gitlab.com/bonzini/qemu : hw/i386: pass RNG seed via setup_data entry hw/rx: pass random seed to fdt hw/mips: boston: pass random seed to fdt hw/nios2: virt: pass random seed to fdt oss-fuzz: ensure base_copy is a generic-fuzzer oss-fuzz: remove binaries from qemu-bundle tree accel/kvm: Avoid Coverity warning in query_stats() docs: Add caveats for Windows as the build platform Signed-off-by:
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Helge Deller authored
When writing back the fd[1] pipe file handle to emulated userspace memory, use sizeof(abi_int) as offset insted of the hosts's int type. There is no functional change in this patch. Signed-off-by:
Helge Deller <deller@gmx.de> Reviewed-by:
Laurent Vivier <laurent@vivier.eu>
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Helge Deller authored
The pipe2() syscall is available on all Linux platforms since kernel 2.6.27, so use it unconditionally to emulate pipe() and pipe2(). Signed-off-by:
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Helge Deller authored
This program: int main(void) { asm("bv %r0(%r0)"); return 0; } produces on real hppa hardware the expected segfault: SIGSEGV {si_signo=SIGSEGV, si_code=SEGV_MAPERR, si_addr=0x3} --- killed by SIGSEGV +++ Segmentation fault But when run on linux-user you get instead internal qemu errors: ERROR: linux-user/hppa/cpu_loop.c:172:cpu_loop: code should not be reached Bail out! ERROR: linux-user/hppa/cpu_loop.c:172:cpu_loop: code should not be reached ERROR: accel/tcg/cpu-exec.c:933:cpu_exec: assertion failed: (cpu == current_cpu) Bail out! ERROR: accel/tcg/cpu-exec.c:933:cpu_exec: assertion failed: (cpu == current_cpu) Fix it by adding the missing case for the EXCP_IMP trap in cpu_loop() and raise a segfault. Signed-off-by:
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- Jul 22, 2022
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Jason A. Donenfeld authored
Tiny machines optimized for fast boot time generally don't use EFI, which means a random seed has to be supplied some other way. For this purpose, Linux (≥5.20) supports passing a seed in the setup_data table with SETUP_RNG_SEED, specially intended for hypervisors, kexec, and specialized bootloaders. The linked commit shows the upstream kernel implementation. At Paolo's request, we don't pass these to versioned machine types ≤7.0. Link: https://git.kernel.org/tip/tip/c/68b8e9713c8 Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: Eduardo Habkost <eduardo@habkost.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Laurent Vivier <laurent@vivier.eu> Reviewed-by:
Jason A. Donenfeld <Jason@zx2c4.com> Message-Id: <20220721125636.446842-1-Jason@zx2c4.com> Signed-off-by:
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Jason A. Donenfeld authored
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to initialize early. Set this using the usual guest random number generation function. This FDT node is part of the DT specification. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by:
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Jason A. Donenfeld authored
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to initialize early. Set this using the usual guest random number generation function. This FDT node is part of the DT specification. I'd do the same for other MIPS platforms but boston is the only one that seems to use FDT. Cc: Paul Burton <paulburton@kernel.org> Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by:
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