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  1. Feb 04, 2023
  2. Feb 03, 2023
    • Peter Maydell's avatar
      Merge tag 'pull-target-arm-20230203' of... · 0730eab4
      Peter Maydell authored
      Merge tag 'pull-target-arm-20230203' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
      
      target-arm queue:
       * Fix physical address resolution for Stage2
       * pl011: refactoring, implement reset method
       * Support GICv3 with hvf acceleration
       * sbsa-ref: remove cortex-a76 from list of supported cpus
       * Correct syndrome for ATS12NSO* traps at Secure EL1
       * Fix priority of HSTR_EL2 traps vs UNDEFs
       * Implement FEAT_FGT for '-cpu max'
      
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      # gpg: Signature made Fri 03 Feb 2023 14:28:59 GMT
      # gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
      # gpg:                issuer "peter.maydell@linaro.org"
      # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
      # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
      # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
      # gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
      # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE
      
      * tag 'pull-target-arm-20230203' of https://git.linaro.org/people/pmaydell/qemu-arm
      
      : (33 commits)
        target/arm: Enable FEAT_FGT on '-cpu max'
        target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
        target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
        target/arm: Implement the HFGITR_EL2.ERET trap
        target/arm: Mark up sysregs for HFGITR bits 48..63
        target/arm: Mark up sysregs for HFGITR bits 18..47
        target/arm: Mark up sysregs for HFGITR bits 12..17
        target/arm: Mark up sysregs for HFGITR bits 0..11
        target/arm: Mark up sysregs for HDFGRTR bits 12..63
        target/arm: Mark up sysregs for HDFGRTR bits 0..11
        target/arm: Mark up sysregs for HFGRTR bits 36..63
        target/arm: Mark up sysregs for HFGRTR bits 24..35
        target/arm: Mark up sysregs for HFGRTR bits 12..23
        target/arm: Mark up sysregs for HFGRTR bits 0..11
        target/arm: Implement FGT trapping infrastructure
        target/arm: Define the FEAT_FGT registers
        target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
        target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
        target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
        target/arm: Move do_coproc_insn() syndrome calculation earlier
        ...
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      0730eab4
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