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riscv: implement Ssqosid extension and sqoscfg CSR
Implement the sqoscfg CSR defined by the Ssqosid ISA extension (Supervisor-mode Quality of Service ID). The CSR contains two fields: - Resource Control ID (RCID) used determine resource allocation - Monitoring Counter ID (MCID) used to track resource usage The CSR is defined for S-mode but accessing it when V=1 shall cause a virtual instruction exception. Implement this behavior by calling the hmode predicate. Link: https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf Signed-off-by:Kornel Dulęba <mindal@semihalf.com> [dfustini: rebase on v8.0.50, reword commit message] Signed-off-by:
Drew Fustini <dfustini@baylibre.com>
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- disas/riscv.c 1 addition, 0 deletionsdisas/riscv.c
- target/riscv/cpu.c 2 additions, 0 deletionstarget/riscv/cpu.c
- target/riscv/cpu.h 3 additions, 0 deletionstarget/riscv/cpu.h
- target/riscv/cpu_bits.h 5 additions, 0 deletionstarget/riscv/cpu_bits.h
- target/riscv/csr.c 34 additions, 0 deletionstarget/riscv/csr.c
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