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    d3651f3d
    hw/riscv: instantiate CBQRI controllers for an example SoC · d3651f3d
    Nicolas Pitre authored and Drew Fustini's avatar Drew Fustini committed
    
    Instantiate a hypothetical CBQRI configuration for testing purposes with
    these properties:
    
      - L2 cache controllers
        - Resource type: Capacity
        - NCBLKS: 12
        - Number of access types: 2 (code and data)
        - Usage monitoring not supported
        - Capacity allocation operations: CONFIG_LIMIT, READ_LIMIT
    
      - Last-level cache (LLC) controller
        - Resource type: Capacity
        - NCBLKS: 16
        - Number of access types: 2 (code and data)
        - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER
        - Event IDs supported: None, Occupancy
        - Capacity allocation ops: CONFIG_LIMIT, READ_LIMIT, FLUSH_RCID
    
      - Memory controllers
        - Resource type: Bandwidth
        - NBWBLKS: 1024
        - MRBWB: 819 (80% of NBWBLKS)
        - Number of access types: 1 (no code/data differentiation)
        - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER
        - Event IDs supported: None, Total read/write byte count, Total
                               read byte count, Total write byte count
        - Bandwidth allocation operations: CONFIG_LIMIT, READ_LIMIT
    
    The memory map for the CBQRI controllers in this example SoC:
    
      Base addr  Size
      0x4820000  4KB  Cluster 0 L2 cache controller
      0x4821000  4KB  Cluster 1 L2 cache controller
      0x4828000  4KB  Memory controller 0
      0x4829000  4KB  Memory controller 1
      0x482A000  4KB  Memory controller 2
      0x482B000  4KB  Shared LLC cache controller
    
    Signed-off-by: default avatarNicolas Pitre <npitre@baylibre.com>
    Signed-off-by: default avatarDrew Fustini <dfustini@baylibre.com>
    d3651f3d
    History
    hw/riscv: instantiate CBQRI controllers for an example SoC
    Nicolas Pitre authored and Drew Fustini's avatar Drew Fustini committed
    
    Instantiate a hypothetical CBQRI configuration for testing purposes with
    these properties:
    
      - L2 cache controllers
        - Resource type: Capacity
        - NCBLKS: 12
        - Number of access types: 2 (code and data)
        - Usage monitoring not supported
        - Capacity allocation operations: CONFIG_LIMIT, READ_LIMIT
    
      - Last-level cache (LLC) controller
        - Resource type: Capacity
        - NCBLKS: 16
        - Number of access types: 2 (code and data)
        - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER
        - Event IDs supported: None, Occupancy
        - Capacity allocation ops: CONFIG_LIMIT, READ_LIMIT, FLUSH_RCID
    
      - Memory controllers
        - Resource type: Bandwidth
        - NBWBLKS: 1024
        - MRBWB: 819 (80% of NBWBLKS)
        - Number of access types: 1 (no code/data differentiation)
        - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER
        - Event IDs supported: None, Total read/write byte count, Total
                               read byte count, Total write byte count
        - Bandwidth allocation operations: CONFIG_LIMIT, READ_LIMIT
    
    The memory map for the CBQRI controllers in this example SoC:
    
      Base addr  Size
      0x4820000  4KB  Cluster 0 L2 cache controller
      0x4821000  4KB  Cluster 1 L2 cache controller
      0x4828000  4KB  Memory controller 0
      0x4829000  4KB  Memory controller 1
      0x482A000  4KB  Memory controller 2
      0x482B000  4KB  Shared LLC cache controller
    
    Signed-off-by: default avatarNicolas Pitre <npitre@baylibre.com>
    Signed-off-by: default avatarDrew Fustini <dfustini@baylibre.com>