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- Feb 22, 2023
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Bjorn Andersson authored
Revert the postponement of clk_disable_unused() for clock providers that implement sync_state, and the change to drivers implementing this, until agreement on the implementation has been reached. This reverts: 29e31415 ("clk: qcom: Remove need for clk_ignore_unused on sc8280xp") 99c0f7d3 ("clk: qcom: sdm845: Use generic clk_sync_state_disable_unused callback") 26b36df7 ("clk: Add generic sync_state callback for disabling unused clocks") Requested-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org>
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- Feb 09, 2023
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Dmitry Baryshkov authored
The GPU clock controller bindings for the Qualcomm sm8350 platform are not correct. The driver uses .fw_name instead of using indices to bind parent clocks, thus demanding the clock-names usage. With the proper clock-names in place, the bindings becomes equal to the bindings defined by qcom,gpucc.yaml, so it is impractical to keep them in a separate file. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Dmitry Baryshkov authored
The gdsc_init() function will rewrite the CLK_DIS_WAIT field while registering the GDSC (writing the value 0x2 by default). This will override the setting done in the driver's probe function. Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe function. Fixes: 453361cd ("clk: qcom: Add graphics clock controller driver for SDM845") Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
The gdsc_init() function will rewrite the CLK_DIS_WAIT field while registering the GDSC (writing the value 0x2 by default). This will override the setting done in the driver's probe function. Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe function. Fixes: 745ff069 ("clk: qcom: Add graphics clock controller driver for SC7180") Reviewed-by:
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Bartosz Golaszewski authored
The binding document is missing the power-domains property. Add it and update the example. Fixes: 0fff9fa0 ("dt-bindings: clock: Add Qualcomm SA8775P GCC") Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by:
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Krzysztof Kozlowski authored
Include asm/cputype.h to fix ARMv7 compile test error: drivers/clk/qcom/clk-cpu-8996.c: In function ‘qcom_cpu_clk_msm8996_acd_init’: drivers/clk/qcom/clk-cpu-8996.c:468:16: error: implicit declaration of function ‘read_cpuid_mpidr’ [-Werror=implicit-function-declaration] Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Bartosz Golaszewski authored
There are four struct definitions in the driver that aren't used so remove them. Reported-by:
kernel test robot <lkp@intel.com> Fixes: ed432b1ed00a ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by:
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Dmitry Baryshkov authored
Extend the list of RPM clocks provided on MSM8996 platform to also include RPM_SMD_XO_CLK_SRC and RPM_SMD_XO_A_CLK_SRC. Fixes: 7066fdd0 ("clk: qcom: clk-smd-rpm: add msm8996 rpmclks") Reviewed-by:
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Dmitry Baryshkov authored
Add CBF clock driver as a part of MSM8996 CPU clocks. Significantly based on AngeloGioacchino del Regno's work at [1]. The CBF is an interconnect between two CPU clusters, setting it up properly is required for booting the MSM8996 with all four cores enabled. [1] https://github.com/sonyxperiadev/kernel/blob/aosp/LE.UM.2.3.2.r1.4/drivers/clk/qcom/clk-cpu-8996.c Co-developed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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- Feb 08, 2023
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Dmitry Baryshkov authored
MSM8996 Core Bus Fabric (CBF) clock controller clocks an interconnect between two CPU clusters. The CBF clock should follow the CPU frequencies to provide enough bandwidth between clusters. Thus a single driver implements both a clock and an interconnect to set the clock rate. Reviewed-by:
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Dmitry Baryshkov authored
Add a simple driver handling the APCS clocks on MSM8996. For now it supports just a single aux clock, linking GPLL0 to CPU and CBF clocks. Note, there is little sense in registering sys_apcs_aux as a child of gpll0. The PLL is always-on. And listing the gpll0 as a property of the apcs would delay its probing until the GCC has been probed (while we would like for the apcs to be probed as early as possible). Signed-off-by:
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- Jan 30, 2023
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Arnd Bergmann authored
In one of the clocks, a redundant initialization for .num_parents got left behind by a recent patch: drivers/clk/qcom/gcc-qcs404.c:63:32: error: initialized field overwritten [-Werror=override-init] 63 | .num_parents = 1, | ^ Fixes: 2ce81afa ("clk: qcom: gcc-qcs404: sort out the cxo clock") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Reviewed-by:
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- Jan 19, 2023
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Dmitry Baryshkov authored
Add missing register writes to CPU clocks setup procedure. This makes it follow the setup procedure used in msm-3.18 kernel. Reviewed-by:
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Dmitry Baryshkov authored
Switch CPU PLLs to use clk_alpha_pll_hwfsm_ops, it seems to suit better. Signed-off-by:
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Dmitry Baryshkov authored
The vendor kernel applies different order while programming SSSCTL and L2ACDCR registers on power and performance clusters. However it was demonstrated that doing this upstream results in the board reset. Make both clusters use the same sequence, which fixes the reset. Signed-off-by:
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Dmitry Baryshkov authored
Switch both power and performance clocks to the GPLL0/2 (sys_apcs_aux) before PLL configuration. Switch them to the ACD afterwards. Signed-off-by:
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Dmitry Baryshkov authored
Initialize ACD configuration from qcom_cpu_clk_msm8996_register_clks(), before registering all clocks. This way we can be sure that the clock is fully configured before letting CCF touch it. Reviewed-by:
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Dmitry Baryshkov authored
Setup all PLLs before registering clocks in the common clock framework. This ensures that the clocks are not accessed before being setup in the known way and that the CCF is in sync with the actual HW programming. Reviewed-by:
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Dmitry Baryshkov authored
- Do not use the Alt PLL completely. Switch to smux when necessary to prevent overvolting - Restore the parent in case the rate change aborts for some reason - Do not duplicate resetting the parent in set_parent operation. Reviewed-by:
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Dmitry Baryshkov authored
Check whether L2 registers contain correct values and skip programming if they are valid. This follows the code present downstream. Reviewed-by:
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Dmitry Baryshkov authored
In some cases the driver might need using GPLL0 to drive CPU clocks. Bring it in through the sys_apcs_aux clock. Reviewed-by:
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Dmitry Baryshkov authored
Current multiplier (60) results in CPU getting the rate which is unlisted in the CPU frequency tables (60 * 19.2 = 1152 MHz). This results in warnings from the cpufreq during startup. Change PLL programming (l = 54) to init CPU clocks to start with the frequency of 54 * 19.2 = 1036.8 MHz which is supported by both power and performance clusters from all speed bins. Signed-off-by:
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Dmitry Baryshkov authored
Change PLL programming to follow the downstream setup. Reviewed-by:
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Dmitry Baryshkov authored
Program PLL_TEST and PLL_TEST_U registers if required by the pll configuration. Signed-off-by:
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Dmitry Baryshkov authored
The MSM8996 CPU clock controller can make use of the sys_apcs_aux clock. Add it to the bindings. Acked-by:
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Taniya Das authored
Add Global Clock Controller (GCC) support for QDU1000 and QRU1000 SoCs. Signed-off-by:
Taniya Das <quic_tdas@quicinc.com> Signed-off-by:
Melody Olvera <quic_molvera@quicinc.com> Reviewed-by:
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Bjorn Andersson authored
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Melody Olvera authored
Add device tree bindings for global clock controller on QDU1000 and QRU1000 SoCs. Signed-off-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "xo" to "xo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "xo_board" clock instead of manually registered "xo" clock and allows us to drop qcom_cc_register_board_clk() call from the driver at some point. In the same way change the looked up system "sleep_clk_src" clock to "sleep_clk", which is registered from DT. Reviewed-by:
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Dmitry Baryshkov authored
SPDM is used for debug/profiling and does not have any other functionality. These clocks can safely be removed. Suggested-by:
Georgi Djakov <djakov@kernel.org> Reviewed-by:
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Dmitry Baryshkov authored
Move clock parent tables down, after the PLL declrataions, so that we can use pll hw clock fields in the next commit. Reviewed-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by:
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Dmitry Baryshkov authored
Add the GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for the multimedia subsystem. Reviewed-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "xo" to "xo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "xo_board" clock instead of manually registered "xo" clock and allows us to drop qcom_cc_register_board_clk() call from the driver at some point. In the same way change the looked up system "sleep_clk_src" clock to "sleep_clk", which is registered from DT. Reviewed-by:
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Dmitry Baryshkov authored
Move PLL clock declarations up, before clock parent tables, so that we can use pll hw clock fields in the next commit. Reviewed-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by:
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Dmitry Baryshkov authored
Define clock/clock-names properties of the MMCC device node to be used on APQ8084 platform. Acked-by:
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Dmitry Baryshkov authored
Add GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for the multimedia subsystem. Acked-by:
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Dmitry Baryshkov authored
Define clock/clock-names properties of the GCC device node to be used on APQ8084 platform. Note: the driver uses a single pcie_pipe clock, however most probably there are two pipe clocks, one from each of PCIe QMP PHYs. Acked-by:
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Robert Marko authored
Having only .name populated in parent_data for clocks which are only globally searchable currently will not work as the clk core won't copy that name if there is no .fw_name present as well. So, populate .fw_name for usb3phy clocks in parent_data as they were missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents"). Fixes: ae55ad32 ("clk: qcom: ipq8074: convert to parent data") Signed-off-by:Robert Marko <robimarko@gmail.com> Reviewed-by:
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