This reverts commit 4c4aba67.

If the IP is U3, the driver will check some USB3 status bits.
This could fail if only USB2 is used.
This only check these bits if USB operate at USB3 speed.

Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
(cherry picked from commit 0c30a5e1)

This add the APU DRM device to mt8365 evk.

Signed-off-by: Alexandre Bailon <abailon@baylibre.com>

Julien Stephan authored 3 years ago and Alexandre Bailon committed 2 years ago

Signed-off-by: Julien STEPHAN <jstephan@baylibre.com>

Currently, we only flush the TLB if the device is active.
But, there is nothing to mark it active.
Don't check if the device is active.

Signed-off-by: Alexandre Bailon <abailon@baylibre.com>

remoteproc try to use iommu_domain_alloc() which doesn't work on
MT8183. Still, we have to configure the IOMMU for this platform.
Even if we can't allocate a domain, we can get one from the platform
driver using iommu_get_domain_for_dev().
But if we set a domain from the platform driver, then the remoteproc
driver may try to release it which will cause a crash or break the
other drivers using the IOMMU.
To avoid that, check if has_iommu is set (required to allocate the
domain) before to try to release the domain.

Note:
We have tried to update the IOMMU driver to support
iommu_domain_alloc() but without success so far.

Signed-off-by: Alexandre Bailon <abailon@baylibre.com>

This adds prepare and unprepare callbacks to fix the VP6 that
stops to work after a suspend to RAM.
In addition, this adds a suspend function that makes sure the
VP6 is not running a firmware while we suspend.
This is required because VP6 suspend / resume is not supported.

Signed-off-by: Alexandre Bailon <abailon@baylibre.com>

By default, remoteproc try to start the APU but most of time,
we want to start it manually, after having changed the name
of the firmware to load.
Disable the auto boot feature.

Signed-off-by: Alexandre Bailon <abailon@baylibre.com>

Julien Stephan authored 3 years ago and Alexandre Bailon committed 2 years ago

this commits prepare the driver to be more generic in order to support
multiple platfomr using the compatible property. To do that, put some
some register values and the clocks names inside private data

Signed-off-by: Julien STEPHAN <jstephan@baylibre.com>

Julien Stephan authored 3 years ago and Alexandre Bailon committed 2 years ago

Signed-off-by: Julien STEPHAN <jstephan@baylibre.com>

Currently, this local APU RAM is not accessible from the CPU.
This workarounds the issue by skiping this section.

Signed-off-by: Alexandre Bailon <abailon@baylibre.com>

The DSP could be debugged using JTAG.
The support of JTAG could enabled at build time and it could be enabled
using debugfs.

Signed-off-by: Alexandre Bailon <abailon@baylibre.com>

The firmware generated by our toolchain contains many empty PT_LOAD
segments. The elf loader don't manage it and will raise an error:
"bad phdr da 0x0 mem 0x0".
To workaround it, implement the sanity_check callback to detect the
empty PT_LOAD segment and change it to PT_NULL.
In that way, the elf load won't try to load the segment.

Signed-off-by: Alexandre Bailon <abailon@baylibre.com>

Implements the interrupt handler to notify virtio about interrupts.

Signed-off-by: Alexandre Bailon <abailon@baylibre.com>

This adds a driver to control the APU present in the MT8183.
This loads the firmware and start the DSP.

Signed-off-by: Alexandre Bailon <abailon@baylibre.com>

Guillaume LA ROQUE authored 3 years ago and Alexandre Bailon committed 2 years ago

This driver support the Startek KD070FHFID015, which is a 7-inch TFT LCD
display using MIPI DSI interface.

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Fabien Parent authored 2 years ago and Alexandre Bailon committed 2 years ago

Add DRM support for MT8365 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Fabien Parent authored 2 years ago and Alexandre Bailon committed 2 years ago

MT8365 requires an additional clock for DPI. Add support for that
additional clock.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

Currently, mtk_dsi_lane_ready (which setup the DSI lane) is triggered
before mtk_dsi_poweron. lanes_ready flag toggle to true during
mtk_dsi_lane_ready function, and the DSI module is set up during
mtk_dsi_poweron.

Later, during panel driver init, mtk_dsi_lane_ready is triggered but does
nothing because lanes are considered ready. Unfortunately, when the panel
driver try to communicate, the DSI returns a timeout.

The solution found here is to put lanes_ready flag to false after the DSI
module setup into mtk_dsi_poweron to init the DSI lanes after the power /
setup of the DSI module.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

MIPI DSI:
- Add "vsys_lcm_reg" regulator support and setup the "mt6357_vsim1_reg",
to power the pannel plugged to the DSI connector.
- Setup the Display Parallel Interface.
  - Add the startek kd070fhfid015 pannel support.

HDMI:
- Add HDMI connector support.
- Add the "ite,it66121" HDMI bridge support, driven by I2C1.
- Setup the Display Parallel Interface.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

- Add aliases for each display components to help display drivers.
- Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals
  for the LED driver of mobile LCM.
- Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane
  output)
- Add the display mutex support.
- Add the following display component support:
  - OVL0 (Overlay)
  - RDMA0 (Data Path Read DMA)
  - Color0
  - CCorr0 (Color Correction)
  - AAL0 (Adaptive Ambient Light)
  - GAMMA0
  - Dither0
  - DSI0 (Display Serial Interface)
  - RDMA1 (Data Path Read DMA)
  - DPI0 (Display Parallel Interface)

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

Add compatible for the MT8365 SoC.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

According to the mtk-mutex.c driver and the SoC DTS, the clock isn't
required to work properly for some of MTK SoC. Improve the clock
requirement by adding a condition which is function to the compatible.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

Display PWM for MT8365 is compatible with MT8183. Then, add MT8365 binding
along with MT8183 SoC.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

According to the Mediatek datasheet, the display PWM block has a power
domain.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

The Startek KD070FHFID015 is a 7-inch TFT LCD display with a resolution
of 1024 x 600 pixels.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

Display Data Path Read DMA for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

Display Overlay for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8192 SoC.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

Display GAMMA for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Fabien Parent authored 2 years ago and Alexandre Bailon committed 2 years ago

DPI for MT8365 is compatible with MT8192 but requires an additional
clock. Modify the documentation to requires this clock only on MT8365 SoCs.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Fabien Parent authored 2 years ago and Alexandre Bailon committed 2 years ago

DPI is part of the display / multimedia block in MediaTek SoCs, and
always have a power-domain (at least in the upstream device-trees).
Add the power-domains property to the binding documentation.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

Display Serial Interface for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

Display Dither for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

Display Color for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

Display Color Correction for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

Add iommu support in the SoC DTS using the 4 local arbiters (LARBs)

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

Local arbiter (LARB) is a component of Smart Multimedia Interface (SMI),
used to help the memory management (IOMMU).
This patch add 4 LARBs and 2 clocks for the larb1 and larb3 support.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

Smart Multimedia Interface (SMI) local arbiter does the arbitration for
memory requests from multi-media engines. Add SMI in the MT8365 DTS will allow
to add local ARBiter (LARB), use by IOMMU.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

The following power domain are added to the SoC dts:
- MM (MultiMedia)
- CONN (Connectivity)
- MFG (MFlexGraphics)
- Audio
- Cam (Camera)
- DSP (Digital Signal Processor)
- Vdec (Video decoder)
- Venc (Video encoder)
- APU (AI Processor Unit)

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Alexandre Mergnat authored 2 years ago and Alexandre Bailon committed 2 years ago

Add binding description for mediatek,mt8365-smi-larb

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>