From e72230f5d027e15d09e836a81fd3adef871e56c2 Mon Sep 17 00:00:00 2001
From: Nicolas Pitre <npitre@baylibre.com>
Date: Tue, 25 Apr 2023 00:13:58 -0700
Subject: [PATCH] hw/riscv: build example SoC when CBQRI_EXAMPLE_SOC enabled
Build the example SoC instantiation code when CBQRI_EXAMPLE_SOC is
enabled.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Signed-off-by: Drew Fustini <dfustini@baylibre.com>
---
hw/riscv/Kconfig | 5 +++++
hw/riscv/meson.build | 1 +
2 files changed, 6 insertions(+)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 8fd4aebc77d..e5892736733 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -49,6 +49,7 @@ config RISCV_VIRT
select PLATFORM_BUS
select ACPI
imply RISCV_CBQRI
+ imply CBQRI_EXAMPLE_SOC
config SHAKTI_C
bool
@@ -88,3 +89,7 @@ config SPIKE
select HTIF
select RISCV_ACLINT
select SIFIVE_PLIC
+
+config CBQRI_EXAMPLE_SOC
+ bool
+ select RISCV_CBQRI
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 2281d17d0b0..50e94f40de4 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -12,5 +12,6 @@ riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')
riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
riscv_ss.add(when: 'CONFIG_RISCV_CBQRI',
if_true: files('cbqri_capacity.c', 'cbqri_bandwidth.c'))
+riscv_ss.add(when: 'CONFIG_CBQRI_EXAMPLE_SOC', if_true: files('cbqri_example_soc.c'))
hw_arch += {'riscv': riscv_ss}
--
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