diff --git a/hw/riscv/cbqri_bandwidth.c b/hw/riscv/cbqri_bandwidth.c
index 27874c6c3c793cb49a468a5eff88867acef35411..661c030782c39c1c4c3c87a14f526e68a2997798 100644
--- a/hw/riscv/cbqri_bandwidth.c
+++ b/hw/riscv/cbqri_bandwidth.c
@@ -384,6 +384,20 @@ static void riscv_cbqri_bc_write_bw_alloc(RiscvCbqriBandwidthState *bc,
     }
 }
 
+static void riscv_cbqri_bc_write_counter_quickhack(RiscvCbqriBandwidthState *bc,
+                                                   uint64_t value)
+{
+    uint32_t mcid = value & 0xfff;
+    if (mcid >= bc->nb_mcids) {
+        return;
+    }
+
+    if (bc->mon_counters[mcid].active) {
+        bc->mon_counters[mcid].ctr_val = value >> 12;
+    }
+}
+
+
 static void riscv_cbqri_bc_write(void *opaque, hwaddr addr,
                                  uint64_t value, unsigned size)
 {
@@ -393,6 +407,9 @@ static void riscv_cbqri_bc_write(void *opaque, hwaddr addr,
     assert(size == 8);
 
     switch (addr) {
+    case (4 * 1024 - 8):
+        riscv_cbqri_bc_write_counter_quickhack(bc, value);
+        break;
     case A_BC_CAPABILITIES:
         /* read-only register */
         break;
diff --git a/hw/riscv/cbqri_capacity.c b/hw/riscv/cbqri_capacity.c
index db11a3c3fc5d9eb2e03face72068cc5ed52b9902..06b12898d67ebc15fedf38c19e0d915b025bbb2f 100644
--- a/hw/riscv/cbqri_capacity.c
+++ b/hw/riscv/cbqri_capacity.c
@@ -373,6 +373,19 @@ static void riscv_cbqri_cc_write_alloc_ctl(RiscvCbqriCapacityState *cc,
     cc->cc_alloc_ctl = value;
 }
 
+static void riscv_cbqri_cc_write_counter_quickhack(RiscvCbqriCapacityState *cc,
+						   uint64_t value)
+{
+    uint32_t mcid = value & 0xfff;
+    if (mcid >= cc->nb_mcids) {
+        return;
+    }
+
+    if (cc->mon_counters[mcid].active) {
+        cc->mon_counters[mcid].ctr_val = value >> 12;
+    }
+}
+
 static void riscv_cbqri_cc_write(void *opaque, hwaddr addr,
                                  uint64_t value, unsigned size)
 {
@@ -382,6 +395,9 @@ static void riscv_cbqri_cc_write(void *opaque, hwaddr addr,
     assert(size == 8);
 
     switch (addr) {
+    case (4 * 1024 - 8):
+        riscv_cbqri_cc_write_counter_quickhack(cc, value);
+        break;
     case A_CC_CAPABILITIES:
         /* read-only register */
         break;